School of Engineering

ENGR 856: Nano-scale Circuits and Systems

Offered in Spring 2006

Class webpage:  (Opens in New Window) Flyer: Download [120 KB]
Instructor: Hamid Mahmoodi URL:  (Opens in New Window)
Office: SCI 130 Email:
Phone: 415-338-6579 Office Hours: TBA
  1. Course Aims and Objectives:

    This course introduces advanced topics in VLSI circuit and system design. High-performance and low-power design issues in modern and future processes are discussed in detail. The challenges of technology scaling are covered and state of the art technologies and solutions at different levels of abstraction are discussed. A class project is an integral part of this course.

    Specific Learning Objectives:
    By the end of this course, students will have the following understanding and skills:

    • Knowledge of silicon technology scaling and trends
    • Knowledge of challenges of technology scaling in nano-scale regimes
    • Applying low power design approaches and techniques at different levels of abstraction
    • Knowledge of challenges associated leakage currents and process variations
    • Developing a new design techniques under excessive leakage and process variations
    • Exploiting non-classical CMOS devices for circuit design in such technologies
    • Knowledge of prospects of future non-silicon nanotechnologies

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  2. Prerequisite:

    Basic knowledge of logic circuits and digital electronics and VLSI which is covered in the following courses:
    ENGR 378: Digital System Design
    ENGR 453: Digital Integrated Circuit Design

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  3. Textbooks:

    Primary textbook:
    Design of High-Performance Microprocessor Circuits, A. Chandrakasan, Bowhill, & Fox, IEEE Press © 2001

    Class notes:
    Lecture notes will be made from the latest presentations made in leading conferences in the field by industry leaders

    Technical Journals and Conferences:
    1) IEEE journal of solid-state circuits
    2) International Conference of Solid-State Circuits (ISSCC)

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  4. Topics:
    1. Technology scaling and trends
    2. CMOS scaling challenges in sub 100nm regimes
    3. Low power design
    4. Energy recovery techniques
    5. Techniques for leakage power reduction
    6. Process variations in devices and interconnects
    7. Circuit design in nano-scaled technologies
    8. Self-timed circuits
    9. High speed VLSI arithmetic units
    10. Emerging memory technologies
    11. SOI technology and circuits

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  5. Grading Policy:

    1 mid-term exam accounting for 30% of the grade
    Project accounting for 70% of the grade

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  6. Accommodations for students with disabilities:

    The Disability Program and Resources Center provides university academic support services and specialized assistance to students with disabilities. Students in need should contact Services for Students with Disabilities (SSB 110, 338-2472) for information regarding accommodation. Please notify your instructor so that reasonable efforts can be made to accommodate you.

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